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cy8cplc10 powerline communication solution cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-50001 rev. *k revised january 6, 2011 features integrated powerline modem phy 2400 bps frequency shift keying modulation powerline optimized network protocol integrates data link, transport, and network layers supports bidirectional half-duplex communication 8-bit crc error detection to minimize data loss i 2 c enabled powerline application layer supports i 2 c frequencies of 50, 100, and 400 khz reference designs for 110v to 240v ac, 12v to 24v ac/dc powerlines reference designs comply with cenelec en50065-1:2001 and fcc part 15 applications residential and commercial lighting control home automation automatic meter reading industrial control and signage smart energy management functional overview the cy8cplc10 is an integrated powerline communication chip with the powerline modem phy and powerline network protocol stack. this chip provides robust communication between different nodes on a powerline. powerline transmitter the application residing on a ho st microcontroller generates messages to be transmitted on the powerline. these messages are delivered to the cy8cplc10 over an i 2 c serial link. the powerline network layer residing on the cy8cplc10 receives these i 2 c messages and generates a powerline trans- ceiver (plt) packet. these packets are modulated by the fsk modem and coupled with powerlin e by the external coupling circuit. powerline receiver powerline signals are received by the coupling circuit and demodulated by the fsk modem phy to reconstruct plt packets. these plt packets are decoded by the powerline network protocol and then transferred to the external host micro- controller in an i 2 c format. logic block diagram cy8cplc10 i 2 c packet ac/dc powerline coupling circuit (110v-240 v ac, 12v-24v ac/dc, etc.) psoc/ external c powerline powerline communication solution application circuitry host system powerline network protocol powerline fsk modem phy [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 2 of 34 contents functional overview ........................................................ 1 powerline transmitter ................................................. 1 powerline receiver ..................................................... 1 logic block diagram ........................................................ 1 robust communication using cypress?s plc solution 3 detailed description ......................................................... 3 powerline modem phy ............................................... 3 powerline network protocol ... ..................................... 4 cy8cplc10 memory map .......................................... 6 external host application .... ...................................... 11 target applications ........................................................ 13 lighting control ......................................................... 13 smart energy management ...................................... 14 automatic meter reading ....... .............. .............. ....... 15 industrial signage ...................................................... 16 pinouts ............................................................................ 17 electrical specifications ................................................ 19 absolute maximum ratings .... ................................... 19 operating temperature ............................................. 19 dc electrical characteristics ..................................... 20 ac electrical characteristics ..................................... 21 packaging information ................................................... 23 thermal impedances ................................................. 23 capacitance on crystal pins ..................................... 23 solder reflow peak temperat ure ............................. 23 evaluation tools ............................................................. 24 cy3272 hv evaluation kit .... .............. .............. ........ 24 cy3273 lv evaluation kit ..... .............. .............. ........ 24 cy3210-miniprog1 .... .............. ............... ........... ........ 24 cy3210-psoceval1 .. .............. ............... ........... ........ 24 cy3214-psocevalusb .. ........... ............ ........... ........ 24 development tools ................. .............. .............. ........... 25 cy3215-dk basic development kit ....... ........... ........ 25 device programmers ............. .................................... 25 ordering information ...................................................... 26 ordering code definitions ..... .................................... 26 acronyms ........................................................................ 27 acronyms used ......................................................... 27 reference documents .................................................... 27 document conventions ......... .................................... 27 units of measure ....................................................... 27 numeric conventions ............ .................................... 27 glossary .......................................................................... 28 document history page ................................................. 33 sales, solutions, and legal information ...................... 34 worldwide sales and design s upport ......... .............. 34 products .................................................................... 34 psoc solutions ................................................................ 34 [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 3 of 34 robust communication using cypress?s plc solution powerlines are one of the most widely available communication mediums for plc technology. the pervasiveness of powerlines also makes it difficult to predict the characteristics and operation of plc products. because of the variable quality of powerline around the world, implementing robust communication over powerline is an engineering challenge. keeping this in mind, cypress's plc solution has been designed to enable secure and reliable communication over po werlines. cypress plc features that enable robust communication over powerline include: integrated powerline phy modem with optimized filters and amplifiers to work with lossy high voltage and low voltage powerlines. powerline optimized network protocol that supports bidirec- tional communication with acknowledgement based signaling. in case of data packet loss due to bursty noise on the powerline, the transmitter can retransmit data. the powerline network protocol also supports 8-bit crc for error detection and data packet retransmission. a carrier sense multiple access (csma) scheme, built into the network protocol, minimizes collisions between packet trans- missions on the powerline. this provides support for multiple masters and reliable communication on a bigger network. detailed description figure 1. cy8cplc10 internal block diagram the cy8cplc10 consists of two main functional components: powerline modem phy powerline network protocol the user application resides on a host system such as psoc ? , ez-color ? , or any other microcontroller. the messages generated by the application are communicated to the cy8cplc10 over i 2 c and processed by these functional components. the following sections present a brief description of each of these components. powerline modem phy figure 2. cy8cplc10: fsk modem phy the physical layer of cypress?s plc solution is implemented using an fsk modem that enab les half duplex communication on a powerline. this modem supports data rates up to 2400 bps. figure 3. cy8cplc10: fs k modem phy block diagram tx buffer memory array rx buffer processor fsk modulator fsk de-modulator i2c interface i2c_scl i2c_sda fsk_out fsk_in status and interrupt signals tx_ led rx_ led biu_ led host _int external 24 mhz clock oscillator (extclk) log_addr[2:0] i2c_addr eeprom external 32.768 khz crystal (xtal_in, xtal_out) clksel pll protocol timer fsk modem clock fsk modem clock cy8cplc10 i 2 c packet powerline network protocol powerline fsk modem phy powerline communication solution network protocol coupling circuit hf band pass filter hysteresis comparator digital receiver if band pass filter low pass filter mixer correlator powerline modem phy modulator local oscillator logic ?1? or logic ?0? square wave at fsk frequencies digital transmitter transmitter receiver local oscillator rx amplifier programmable gain amplifier external low pass filter [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 4 of 34 transmitter section digital data from the network layer is serialized by the digital transmitter and fed as input to the modulator. the modulator divides the local oscillator frequency by a definite factor depending on whether the input data is high level logic ?1? or low level logic ?0?. it then generates a sine wave at 133.3 khz (logic ?0?) or 131.8 khz (logic ?1?), which is fed to the programmable gain amplifier to generate fsk mo dulated signals. the logic ?1? frequency can also be configured as 130.4 khz for wider fsk bandwidth. receiver section the incoming fsk signal from the powerline is input to a high frequency (hf) band pass filt er that filters out-of-band frequency components and outputs filtered signal within the desired spectrum of 125 khz to 140 khz for further demodu- lation. the mixer block multiplies the filtered fsk signals with a locally generated signal to produce heterodyned frequencies. the intermediate frequency (if) band pass filters further remove out-of-band noise as required for further demodulation. this signal is fed to the correlator which produces a dc component (consisting of logic ?1? and ?0?) and a higher frequency component. the output of the correlator is f ed to an external low pass filter with a cut-off frequency of 7.5 khz. the signal is then fed to the internal low pass filter (lpf) t hat outputs only the demodulated digital data at 2400 baud and suppresses all other higher frequency components generated in the correlation process. the output of the lpf is digitized by the hysteresis comparator. this eliminates the effects of correlat or delay and false logic triggers due to noise. the digital receiver deserializes this data and outputs to the network layer for interpretation. coupling circuit reference design the coupling circuit couples low voltage signals from cy8cplc10 to the powerline. the topology of this circuit is determined by the voltage on the powerline and design constraints mandated by po werline usage regulations. cypress provides reference designs for a range of powerline voltages such as 110v ac, 240v ac, 12v dc, 12v ac, 24v dc, and 24v ac. the cy8cplc10 is capable of data communication over other ac/dc powerlines as well with the appropriate external coupling circuit. the 110v ac and 240v ac designs are compliant to the following powerline usage regulations: fcc part 15 for north america en50065-1:2001 powerline network protocol cypress?s powerline optimized network protocol performs the functions of the data link, network, and transport layers in an iso/osi equivalent model. figure 4. cy8cplc10: powerline network protocol the network protocol implemented on the cy8cplc10 chip supports the following features: bidirectional half-duplex communication master and slave as well as peer-to-peer network of powerline nodes multiple masters on powerline network 8-bit logical addressing supports up to 256 powerline nodes 16-bit extended logical addressing supports up to 65536 powerline nodes 64-bit physical addressing supports up to 2 64 powerline nodes individual broadcast or group mode addressing carrier sense multiple access (csma) full control over transmission parameters ? acknowledged ? unacknowledged ? repeated transmit ? sequence numbering csma and timing parameters csma: the protocol provides th e random selection of a period between 85 and 115 ms (out of seven possible values in this range) in which the band in use de tector must indicate that the line is not in use, before attempting a transmission. after completing a transmission when band-in-use is enabled for the system, the application should wait 125 ms before the next transmission. cy8cplc10 i 2 c packet powerline network protocol powerline fsk modem phy powerline communication solution [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 5 of 34 band-in-use (biu): a band-in-use detector, as defined under cenelec en 50065-1, is active whenever a signal that exceeds 86 dbuvrms in the range 131.5 khz to 133.5 khz is present for at least 4 ms. this threshold can be configured for different end-system applicatio ns not requiring cenelec compliance.the modem tries to retransmit after every 85 to 115 ms when the band is in use. the transmitter times out after 1.1 seconds to 3 seconds ( depending on the noise on the powerline) and generates an interr upt to indicate that the trans- mitter was unable to acquire the powerline. powerline transceiver packet the powerline network protocol defines a powerline trans- ceiver (plt) packet structure, which is used for data transfer between nodes across the powerline. packet formation and data transmission across the powerline network is implemented inter- nally in cy8cplc10. a plt packet is apportioned into a variable length header (minimum 6 bytes to maximum 20 bytes, depending on address type), a variable length payload (minimum 0 bytes to maximum 31 bytes), and a packet crc byte. this packet (preceded by a one byte preamble "0xab") is then transmitted by the powerline modem phy and the external coupling circuit across the powerline. the format of the plt packet is shown in ta b l e 1 . table 1. powerline transceiver (plt) packet structure packet header the packet header comprises the first six bytes of the packet when 1-byte logical addressing is used. when 8-byte physical addressing is used, the source and destination addresses each contain eight bytes. in this ca se, the header can consist of a maximum of 20 bytes. unused fields marked rsvd are for future expansion and are transmitted as bit 0. ta b l e 2 describes the plt packet header fields in detail. table 2. powerline transceiver (plt) packet header payload the packet payload has a length of 0 to 31 bytes. payload content is user defined and c an be read or written through i 2 c. packet crc the last byte of the packet is an 8-bit crc value used to check packet data integrity. this crc calculation includes the header and payload portions of the packet and is in addition to the powerline packet header crc. sequence numbering the sequence number is increased for every new unique packet transmitted. if in acknowledged mode and an acknowledgment is not received for a given packet, that packet is re-transmitted (if tx_retry > 0) with the same sequence number. if in unacknowledged mode, the packet is transmitted (tx_retry + 1) times with the same sequence number. if the receiver receives consecutive packets from the same source address with the same sequence number and packet crc, it does not notify the host of the duplicate packet reception. if in acknowledged mode, it still sends an acknowledgment so that the transmitter knows that the packet was received. addressing the logical address of the plc node is set through software by the external host controller or by a remote node on the powerline. the logical address can also be set through hardware with the 3-bit log_addr (logical address) port (for example, an on-board 3-bit dip switch). however, it is overwritten when set in software. every cy8cplc10 chip also has a unique 64-bit physical address which can be used for assigning the logical addresses. byte offset bit offset 765432 1 0 0x00 sa type da type service type rsvd response rsvd 0x01 destination address (8-bit logical, 16-bit extended logical or 64-bit physical) 0x02 source address (8-bit logical, 16-bit extended logical or 64-bit physical) 0x03 command 0x04 rsvd payload length 0x05 seq num powerline packet header crc 0x06 payload (0 to 31 bytes) powerline transceiver packet crc field name no. of bits tag description sa type 1 source address type 0 - logical addressing 1- physical addressing da type 2 destination address type 00 - logical addressing 01 - group addressing 10 - physical addressing 11 - invalid service type 1 0 - unacknowledged messaging 1 - acknowledged messaging response 1 response 0 - not an acknowledgement or response packet 1 - acknowledgement or response packet seq num 4 sequence number four bit unique identifier for each packet between source and destination header crc 4 four bit crc value. this enables the receiver to suspend receiving the rest of the packet if its header is corrupted [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 6 of 34 all the address pins are logically inverted, that is, applying a high voltage on these pins corresponds to writing a logic ?0? and vice versa. group membership group membership enables the user to multicast messages to select groups. the cy8cplc10 supports two types of group addressing. single group membership: the network protocol supports up to 256 different groups on the network in this mode. in this mode, each plc node can only be part of a single group. for example, multiple plc nodes can be part of group 131. multiple group membership: the network protocol supports eight different groups in this mode and each plc node can be a part of multiple groups. for example, a single plc node can be a part of group 3, group 4, and group 7at the same time. both these modes can also be used together for group membership. for example, a single plc node can be a part of group 131 and also multiple groups such as group 3, group 4, and group 7. the group membership id for broadcasting messages to all nodes in the network is 0x00. the service type is always set to unacknowledgment mode in group addressing mode. this is to avoid acknowledgment flooding on the powerline during multicast. cy8cplc10 memory map ta b l e 3 gives the detailed cy8cplc10 memory location infor- mation. this information can be used for application devel- opment on an external host controller. several plc commands are instantiated from the powerline network protocol based on which memory location is written. table 3. cy8cplc10 memory map offset register name access 7 6 5 4 3 2 1 0 0x00 int_enable rw int_clear int_polarity int_unableto tx int_tx_ no_ack int_tx_ no_resp int_rx_ packet_ dropped int_rx_ data_ available int_tx_ data_ sent 0x01 local_la_lsb rw 8 - bit logical address/lsb for extended 16-bit address 0x02 local_la_msb rw msb for extended 16-bit address 0x03 local_group rw 8-bit group address 0x04 local_group_ hot rw one hot encoded (e.g. if byte = 0b00010001, then member of groups #5 and #1) 0x05 plc_mode rw tx_enable rx_enable lock_ configuration disable_ biu rx_ overwrite set_ext_ address promiscuous _mask promiscuous _crc_mas k 0x06 tx_message_ length rw send_ message reserved payload_length_mask 0x07 tx_config rw tx_sa_ type tx_da_type tx_service _type tx_retry 0x08 tx_da rw remote node destination address (8 bytes) 0x10 tx_commandid rw tx command id 0x11 tx_data rw tx data (31 bytes) 0x30 threshold_noise rw reserved auto_biu_ threshold reserved biu_threshold_constant 0x31 modem_config rw reserved tx_delay reserved modem_f skbw_ma sk reserve d modem_bps_mask 0x32 tx_gain rw reserved tx_gain 0x33 rx_gain rw reserved rx_gain 0x34-0x3f reserved rw reserved 0x40 rx_message_ info rnew_rx_ msg rx_da_ type rx_sa_ type rx_msg_length 0x41 rx_sa r remote node source address (8 bytes) 0x49 rx commandid r rx command id 0x4a rx_data r rx data (31 bytes) 0x69 int_status r status_valu e_change reserved status_busy status_tx_ no_ack status_tx _ no_resp status_ rx_pack et_dropp ed status_rx_ data_availab le status_tx_d ata_ sent 0x6a local_pa r physical address (8 bytes), "0x6a -> msb" 0x72 local_fw r version number [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 7 of 34 ta b l e 4 gives the description of the various fields outlined in table 3 on page 6. [1] table 4. memory field description field name no. of bits description int_enable register (0x00) for the host_int pin int_clear 1 0 - int cleared (w) 1 - int triggered (set internally) note: the user should set this bit to logic 0 after reading the int_status register. this clea rs the int_status register, except for status_rx_packet_dropped and status_rx_data_available. int_polarity 1 0 - active high 1 - active low int_unabletotx 1 enable interrupt for biu timeout and the modem is unable to transmit if disable biu = 0 int_tx_no_ack 1 enable interrupt for no acknowledgment received if service type = 1 (ack mode) int_tx_no_resp 1 enable interrupt for no response received int_rx_packet_dropped 1 enable interrupt when rx packet is dropped because rx buffer is full. note: if there is a prior status change that hasn't been cleared (status_value_change = '1') when an rx packet is dropped, the host_int pin will be asserted regardless of the value of this bit. int_rx_data_available 1 enable interrupt when rx buffer has new data. note: if there is a prior status change that hasn't been cleared (status_value_change = '1') when a new message is received, the host_int pin w ill be asserted regardless of the value of this bit. int_tx_data_sent 1 enable interrupt when tx data is sent successfully plc_mode register (0x05) tx_enable 1 0 - tx disabled (can send acks only) 1 - tx enabled rx_enable 1 0 - rx disabled (can receive acks only) 1 - rx enabled lock_configuration 1 0 - allow remote access to change config (tx enable, ext address, disable biu, threshold value, logical address, group membership) 1 - lock remote access to change config disable_biu 1 0 - enables band-in-use 1 - disables band-in-use rx_overwrite 1 0 - if rx buffer is full, new rx message is dropped 1 - if rx buffer is full, new rx message overwrites rx buffer set_ext_address 1 0 - 8-bit addressing mode 1 - extended 16-bit addressing mode note: this mode should be the same in all the devices in the network promiscuous_mask 1 0 - drops the rx message if destination address does not match the local address 1- ignores destination address match and accepts all crc-verified rx messages promiscuous_crc_mask 1 0 - drops the rx message if the 8-bit packet crc fails 1- ignores the 8-bit packet crc and accepts all rx messages if destination address matches local address tx_message_length register (0x06) [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 8 of 34 send_message 1 0 - transmitter is idle. automatically cleared after each transmit 1 - triggers the transmit to send message in tx data across powerline note: the registers tx config, tx destination address, tx command id and tx data need to be set before the user sets this bit to logic 1 payload_length_mask 5 5-bit value for variable payload length. the payload length can vary from 0 to 31. tx_config register(0x07.) tx_sa_type 1 0 - logical address 1 - physical address tx_da_type 2 00 - logical address 01 - group address 10 - physical address 11 - invalid tx_service_type 1 0 - unacknowledgement mode 1 - acknowledgement mode tx_retry 4 4-bit value for variable tx retry count tx_da register (0x08 - 0x0f) 8-bit logical address 0x08 16-bit logical address 0x08 - lsb 0x09 - msb 64-bit physical address 0x08 - msb | 0x0f - lsb threshold_noise register (0x30) auto_biu_threshold 1 0 - auto set threshold is disabled 1 - auto set threshold is enabled. this state overrides the threshold values in register 0x30. biu_threshold_constant 3 000 - 70 dbuvrms 001 - 75 dbuvrms 010 - 80 dbuvrms 011 - 87 dbuvrms (default) 100 - 90 dbuvrms 101 - 93 dbuvrms 110 - 96 dbuvrms 111 - 99 dbuvrms modem_config register (0x31) tx_delay 2 00 - 7 ms 01 - 13 ms 10 - 19 ms 11 - 25 ms modem_fsk_bw_mask 1 0 - logic '0' - 133.3 khz logic '1' - 131.8 khz 1 - logic '0' - 133.3 khz logic '1' - 130.4 khz modem_bps_mask 2 00 - 600 bps [1] 01 - 1200 bp [1] 10 - 1800 bps 11 - 2400 bps (default) tx_gain register (0x32) table 4. memory field description (continued) field name no. of bits description [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 9 of 34 tx_gain 4 the following values are t he output ac voltage swing for the given settings: 0000 - 55 mvp-p 0001 - 75 mvp-p 0010 - 100 mvp-p 0011 - 125 mvp-p 0100 - 180 mvp-p 0101 - 250 mvp-p 0110 - 360 mvp-p 0111 - 480 mvp-p 1000 - 660 mvp-p 1001 - 900 mvp-p 1010 - 1.25 vp-p 1011 - 1.55 vp-p (default) 1100 - 2.25 vp-p 1101 - 3.00 vp-p 1110 - 3.50 vp-p 1111 - reserved rx_gain register (0x33) rx_gain 3 the following values are t he minimum rx input sensitivity for the given settings: 000 - 5 mvrms (default) 001 - 5 mvrms 010 - 2.5 mvrms 011 - 1.25 mvrms 100 - 600 vrms 101 - 350 vrms 110 - 250 vrms 111 - 125 vrms rx_message_info register (0x40) new_rx_msg 1 0 - no packet received 1 - new packet received note: user sets this bit to logic 0 after reading the rx message. this allows the de vice to receive a new rx message. this also clears the status_value_change, status_rx_packet_dropped, and status_rx_data_available bits in the int_status register. rx_da_type 1 0 - logical / physical addressing 1 - group addressing rx_sa_type 1 0 - logical address 1 - physical address rx_msg_length 5 5-bit value for variable payload length. the payload length can vary from 0 to 31. rx_sa register (0x41 - 0x48) 8-bit logical address 0x41 16-bit logical address 0x41 - lsb 0x42 - msb 64-bit physical address 0x41 - msb | 0x48 - lsb int_status register (0x69) note: when the user sets int_clear to logic 0, every bi t in this register (except status_rx_packet_dropped and status_rx_data_available) will be cleared to logic 0. when the user sets new_rx_msg, the status_value_change, status_rx_packet_dropped and status_rx_data_available bits will be cleared to logic 0. table 4. memory field description (continued) field name no. of bits description [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 10 of 34 status_value_change 1 0 - no change 1 - change status_busy 1 0 - no biu timeout 1 - biu timeout or transmission is attempted when tx_enable = 0 status_tx_no_ack 1 if service type = 1 (ack mode) 0 - ack received (when tx data sent = 1) 1 - no ack received (when tx data sent = 0) note: the timeout window for receiving the ack is 500ms status_tx_no_resp 1 0 - response received (when tx data sent = 1) 1 - no response received (when tx data sent = 0) note:the timeout window for receiving responses is 1.5s status_rx_packet_dropped 1 if rx overwrite = 0 0 - no rx packet is dropped 1- rx packet is dropped because rx buffer is full status_rx_data_available 1 0 - no new data available in rx buffer 1- rx buffer has new data available status_tx_data_sent 1 0 - no tx data sent 1- tx data sent successfully table 4. memory field description (continued) field name no. of bits description note 1. to ensure that the receiver has sufficient time to start up and read the first byte, the transmit delay parameter (modem_txde lay) should be set to >= 18 ms for 600 bps and >= 12 ms for 1200 bps. for 1800 bps and 2400 bps, the delay can be set to any value. [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 11 of 34 external host application the application residing on the external host microcontroller has direct access to the lo cal plc memory over i 2 c. the i 2 c commu- nication enables the host controller to instantiate several plc functions by reading or writing to the appropriate memory locations in the plc chip. thus the host application can configure the cy8cplc10, read status and configuration infor- mation, and transmit data to remote powerline nodes. refer to the cy8cplc10 application note (an52478 at http://www.cypress.com ) on how to build a plc command set using the cy8cplc10 memory map. the device has a dedicated pin (i2c_addr) for selecting the i 2 c slave address while communicating with the external controller. the two i 2 c slave addresses available are 0x01 and 0x7a. remote commands in addition to sending normal data over the powerline, the cy8cplc10 can also send (and request) control information to (and from) another node on the network. the type of remote command to transmit is set by the tx_commandid register and when received, is stored in the rx_commandid register. when a control command (command id = 0x01 - 0x08 and 0x0c - 0x0f) is received, the protocol automatically processes the packet (if lock_configuration is '0'), responds to the initiator, and notifies the host of the successful transmission and reception. when the send data command (id 0x09) or request for data command (id 0x0a) is received, the protocol replies with an acknowledgment packet (if tx_service_type = '1'), and notifies the host of the new received data . if the initiator does not receive the acknowledgment packet within 500 ms, it notifies the host of the ?no acknowledgment received? condition. when a response command (id 0x0b) is received by the initiator within 1.5s of sending the request for data command, the protocol notifies the host of the successful transmission and reception. if the response command is not received by the initiator within 1.5s, it notifi es the host of the no response received condition. the host is notified by updating the appropriate values in the int_status register (including status_value_change) and asserting the host_int pin (if the corresponding bit is set in the int_enable register). the command ids 0x30-0xff can be used for custom commands that will be processed by the exte rnal host (for example, set an led color, get a temperature/voltage reading). the available remote commands are described in table 5 with the respective command ids. eeprom back up for remote reset the device also has an eeprom to back up memory registers 0x00-0x05 and 0x30-0x33. when the device is reset remotely by the setremote_reset command (described in ta b l e 5 ), it clears its memory map and loads from the eeprom and returns to idle mode. table 5. remote commands cmd id command name description payload (tx data) response (rx data) 0x01 setremote_txenable sets the tx enable bit in the plc mode register. rest of the plc mode register is unaffected 0 - disable remote tx 1 - enable remote tx if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x02 setremote_reset reset the remote node configuration none if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x03 setremote_extendedaddr set the addressing to extended addressing mode 0 - disable extended addressing 1 - enable extended addressing if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x04 setremote_logicaladdr assigns the specified logical address to the remote plc node if ext address = 0, payload = 8-bit logical address if ext address = 1, payload = 16-bit logical address if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x05 getremote_logicaladdr get the logical address of the remote plc node none if remote tx enable = 0, response = none if remote tx enable = 1, {if ext address = 0, response = 8-bit logical address if ext address = 1, response = 16-bit logical address} [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 12 of 34 0x06 getremote_physicaladdr get the physical address of the remote plc node none if remote tx enable = 0, response = none if remote tx enable = 1, response = 64-bit physical address 0x07 getremote_state request plc_mode register content from a remote plc node none if remote tx enable = 0, response = none if remote tx enable = 1, response = remote plc mode register 0x08 getremote_version get the version number of the remote node none if tx enable = 0, response = none if tx enable = 1, response = remote version register 0x09 sendremote_data transmit data to a remote node. payload = local tx data if local service type = 0, response = none if local service type = 1, response = ack 0x0a requestremote_data request data from a remote node payload = local tx data if local service type = 1, response = ack then, the remote node host must send a responseremote_data command. the response must be completely transmitted within 1.5s of receiving the request. otherwise, the requesting node will time out. 0x0b responseremote_data transmit response data to a remote node. payload = local tx data none 0x0c setremote_biu enables/disables biu function- ality at the remote node 0 - enable remote biu 1 - disable remote biu if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x0d setremote_thresholdvalue sets the threshold value at the remote node 3-bit remote threshold value if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x0e setremote_groupmembership sets the group membership of the remote node byte0 - remote single group membership address byte1- remote multiple group membership address if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x0f getremote_groupmembership ge ts the group membership of the remote node none if remote tx enable = 0, response = none if remote tx enable = 1, response = byte0 - remote single group membership address byte1- remote multiple group membership address 0x10 - 0x2f reserved 0x30 - 0xff user defined command set table 5. remote commands (continued) cmd id command name description payload (tx data) response (rx data) [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 13 of 34 target applications lighting control cy8cplc10 enables control of incandescent, sodium vapor, fl uorescent, and led lighting fixtur es over existing powerlines. cypress?s powerline communication solution easily integrates with wall-switch dimmers and lamp and appliance modules, enabling on and off, dimming, color mixing, and tunable white light control. the cy8cplc10 can control indi vidual or a group of lighting fixtures in a home or a commercial building. elaborate lighting scenes ca n be created using application software. household lighting fix tures can also be programmed to turn on and off at user def ined intervals using a pc based graphical user interface. figure 5. powerline communication for home lighting figure 6. powerline communication for pool lighting ? [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 14 of 34 smart energy management using the cy8cplc10, individual panels in a solar array can tr ansmit diagnostic data over the ex isting dc powerlines. an array diagnostic unit controller can communicate with individual solar panels to probe specific diagnostic information. when the diag nostic data is collected by the controller, it is transmitted across the powerline to a data monitoring console. this makes it possibl e to acquire and transmit real time data regarding energy output of individua l panels to the array controller and subsequently even to a sol ar farm control station over the powerline. figure 7. powerline communication for sm art energy management (solar diagnostics) [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 15 of 34 automatic meter reading the cy8cplc10 can be designed in electric meters in household and industrial environments to transmit power usage information to a centralized billing system. the cypress powerline communica tion solution is ideally suited to handle multiple data sources because of the in-built network protocol sta ck that enables individual addressing of mu ltiple nodes on the same powerline. in p hysical addressing mode, up to 2 64 power meters can transmit usage statistics to the local billing center. application layer software can be used to provide real time usage statistics to a customer. ener gy utilities can improve customer service and control meter readi ng costs, especially in areas where accessing meters is difficult or unsafe, while making the invoicing process more efficient. figure 8. powerline communicati on for automati c meter reading [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 16 of 34 industrial signage an entire array of new convenience and adv anced control features are available in aut omobiles today. it is projected that a hig h feature content car cannot have enough space to contain multiple wiri ng segments and connectors without compromising power loss and safety. one solution is to reduce the number of cables by using existing powerline as the transmission medium of digital contro l signals. the cy8cplc10 enables control of automotive led strobe, beacon, tail lights, and indicators over the existing direct current (d c) 12v to 42v battery powerline. combined with cypress?s ez-color lighting solution, dimming and color mixing of led based automot ive lighting fixtures in applications such as mobile led displays is possible. figure 9. powerline communication for industrial signage [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 17 of 34 pinouts figure 10. cy8cplc10 28-pin ssop note 2. reserved pins must be left unconnected. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vdd fsk_ out clksel i2c_scl i2c_sda xtal_in xtal_ out rxcomp _out i2c_ addr rsvd rsvd host_int agnd rxcomp _in fsk_in reset biu_ led rx_ led tx_ led rsvd tx_ shutdown log_ addr_0 log_ addr_1 log_ addr_2 rsvd xtal_ stablity vss extclk table 6. pin definitions pin number pin name i/o description 1 rx_led output rx indicator led 2 rsvd reserved reserved pin [2] 3 fsk_out analog output analog fsk output. this signal is coupled to the powerline through an external coupling circuit 4 clksel input (internal pull up) fsk mo dem clock source select logic ?0? ? external clock oscillator (extclk) selected logic ?1? ? external crystal (xtal_in, xtal_out) selected note: the external crystal (xtal_in, xtal_out) is always required for the protocol timing. 5 tx_shutdown output output to disable extern al transmit circuitry during receive mode. logic ?0? - when the modem is transmitting logic ?1? - when the modem is not transmitting 6 log_addr_0 input (interna l pull up) connected to the least significant bit of the 3-bit logical address. this is an inverted pin; applying a high voltage on this pin corresponds to writing a logic ?0? and vice versa. 7 log_addr_1 input (interna l pull up) connected to the 2nd most significant bit of the 3-bit logical address. this is an inverted pin; applying a high voltage on this pin corresponds to writing a logic ?0? and vice versa. 8 log_addr_2 input (interna l pull up) connected to the most significant bit of the 3-bit logical address. this is an inverted pin; applying a high voltage on this pin corresponds to writing a logic ?0? and vice versa. 9 rsvd reserved reserved pin [2] 10 i2c_scl input i 2 c serial clock 11 i2c_sda input/output i 2 c serial data [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 18 of 34 12 xtal_stability input/o utput external crystal stability. connect a 0.1 uf capacitor between the pin and vss. 13 xtal_in input external crystal i nput. this is the input clock from an external crystal oscil- lator. this crystal is always required for protocol timing. 14 vss ground ground 15 xtal_out output external crystal output. this pin is used along with xtal_in to connect to the external oscillator. this crystal is always required for protocol timing. 16 tx_led output tx indicator led 17 extclk input optional external 24 mhz clock oscillator input for plc modem. 18 biu_led output biu indicator led 19 reset reset reset pin 20 rxcomp_out analog output analog output to the external low pass filter circuitry. 21 rxcomp_in analog input analog input from the external low pass filter circuitry 22 agnd ground analog ground. connect a 1. 0 uf capacitor between the pin and vss. 23 host_int output interrupt output to host cont roller. polarity and enable are configured by the int_enable register. 24 rsvd reserved reserved pin [2] 25 rsvd reserved reserved pin [2] 26 i2c_addr input (internal pu ll up) set i2c slave address. when high - slave address ?0x01? when low - slave address ?0x7a? 27 fsk_in input analog fsk input.this is the input signal from the powerline. 28 vdd power supply voltage. 5v 5% table 6. pin definitions (continued) pin number pin name i/o description [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 19 of 34 electrical specifications this section presents the dc and ac electr ical specifications of the cy8cplc10 plc device. for the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com. absolute maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. operating temperature table 7. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 c higher storage temperatures reduces data retention time. recom- mended storage temperature is +25 c 25 c. extended duration storage temperatures above 65 c degrades reliability. t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied -40 ? +85 c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tristate vss - 0.5 ? vdd + 0.5 v i mio maximum current into any input/output pin -25 ? +50 ma i maio maximum current into any input/output pin configured as analog driver -50 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 8. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 c t j junction temperature -40 ? +100 c the temperature rise from ambient to junction is package specific. see thermal impedances on page 23.the user must limit the power consumption to comply with this requirement. [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 20 of 34 dc electrical characteristics dc power supply the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c. typical parameters apply to 5v at 25 c and are for design guidance only. dc i/o specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c. typical parameters apply to 5v at 25 c and are for design guidance only. dc modem specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c. typical parameters apply to 5v at 25 c and are for design guidance only. table 9. dc power supply symbol description min typ max units notes v dd supply voltage 4.75 ? 5.25 v i dd (tx mode) supply current (tx mode) 30 ma conditions are 5.0v, t a = 25 c i dd (rx mode) supply current (rx mode) 41 ma conditions are 5.0v, t a = 25 c table 10. dc i/o specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v ioh = 10 ma v ol low output level ? ? 0.75 v iol = 25 ma i oh high level source current 10 ? ? ma voh = vdd-1.0v. see the limitations of the total current in the note for voh. i ol low level sink current 25 ? ? ma vol = 0.75v. see the limitations of the total current in the note for vol. v il input low level ? ? 0.8 v v ih input high level 2.1 ? v v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf pin dependent. temp = 25 c. c out capacitive load on pins as output ? 3.5 10 pf pin dependent. temp = 25 c. table 11. dc modem specifications symbol description min typ max units notes v fsk_outdc fsk_out dc voltage v dd /2 v v fsk_indc fsk_in dc voltage v dd /2 v [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 21 of 34 dc i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c. typical parameters apply to 5v at 25 c and are for design guidance only. ac electrical characteristics ac chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c. typical parameters apply to 5v at 25 c and are for design guidance only. ac modem specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c. typical parameters apply to 5v at 25 c and are for design guidance only. ac i/o specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c. typical parameters apply to 5v at 25 c and are for design guidance only. table 12. dc i 2 c specifications parameter description min typ max units notes v ili2c [3] input low level ? ? 0.25 v dd v4.75 v v dd 5.25 v v ihi2c [3] input high level 0.7 v dd ?? v4.75v v dd 5.25 v note 3. all gpios meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections.the i 2 c gpio pins also meet the mentioned specs. table 13. ac chip-level specifications symbol description min typ max units notes f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. t xrst external reset pulse width 10 ? ? s sr power_up power supply slew rate ? ? 250 v/ms vdd slew rate during power up. t powerup time from end of por to readiness for plc and i2c communication ? 1.25 ? s power up from 0v. table 14. ac modem specifications symbol description min typ max units notes v fsk_outh2 _125mv fsk_out second harmonic (fundamental = 125 mvp-p) ? ?32 ? db c v fsk_outh3 _125mv fsk_out third harmonic (fundamental = 125 mvp-p) ? ?9 ? db c v fsk_outh2 _1.55v fsk_out second harmonic (fundamental = 1.55vp-p) ? ?34 ? db c v fsk_outh3 _1.55v fsk_out third harmonic (fundamental = 1.55vp-p) ? ?15 ? db c v fsk_inmax maximum fsk_in signal ? v dd ? vp-p table 15. ac i/o specifications symbol description min typ max units [4] notes trises rise time, cload = 50 pf 10 27 ? ns 10% - 90% tfalls fall time, cload = 50 pf 10 22 ? ns 10% - 90% [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 22 of 34 figure 11. i/o timing diagram ac i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, respectively. typical para meters apply to 5v at 25 c and are for design guidance only. figure 12. definition for timing on the i 2 c bus packaging dimensions table 16. ac characteristics of the i 2 c sda and scl pins symbol description fast-mode units notes min max f scli2c scl clock frequency 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 0.6 ? s t lowi2c low period of the scl clock 1.3 ? s t highi2c high period of the scl clock 0.6 ? s t sustai2c setup time for a repeated start condition 0.6 ? s t hddati2c data hold time 0 ? s t sudati2c data setup time 100 [5] ?ns t sustoi2c setup time for stop condition 0.6 ? s t bufi2c bus free time between a stop and start condition 500 ? s t spi2c pulse width of spikes are suppressed by the input filter. 0 50 ns tfallf tfalls tris ef trises 90% 10% gpio pin output voltage notes 4. 50 ns minimum input pulse width is based on the inpu t synchronizers running at 24 mhz (42 ns nominal period ) 5. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal . if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is relea sed. i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 23 of 34 packaging information this section illustrates the packaging specifications for the cy8cplc10 plc device, along with the thermal impedances for the package and the typical package capacitance on crystal pins. figure 13. 28-pin (210-mil) ssop thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. 51-85079 *d table 17. thermal impedances per package [7] package typical ja [6] typical jc 28 ssop 94 c/w 29 c/w table 18. typical package capacitance on crystal pins package package capacitance 28 ssop 2.8 pf notes 6. t j = t a + power x ja 7. to achieve the thermal impedance specified for the qfn package,r efer to "application notes for surface mount assembly of amko r's microleadframe (mlf) packages" available at http://www.amkor.com . table 19. solder reflow peak temperature package maximum peak temperature time at maximum peak temperature 28 ssop 260 c 20 s [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 24 of 34 evaluation tools cy3272 hv evaluation kit the cy3272 kit is for evaluating, prototyping, and development with the cy8cplc10. the i 2 c interface enables users to develop applications on an external micro in order to commu- nicate over powerline. the hardware comprises of the high voltage coupling circuit for 110v ac to 230v ac powerline which is compliant with the cenelec/fcc standards. this board also has an on-board switch mode power supply. the kit comprises: one high voltage (110 to 240v ac) plc board. user may want to purchase two cy3272 to set up a two-node plc subsystem for evaluation and development cy8cplc10-28pvxi (28ssop) software cd supporting literature cy3273 lv evaluation kit the cy3273 kit is for evaluating, prototyping and development with the cy8cplc10. the i 2 c interface enables users to develop applications on an external micro in order to commu- nicate over powerline. the hardware comprises of the low voltage coupling circuit for 12 to 24v ac/dc powerline. this board also has a linear power supply. the kit comprises: one low voltage (12-24v ac/dc) plc board. user may want to purchase two cy3273 to setup a two-node plc subsystem for evaluation and development. cy8cplc10-28pvxi (28ssop) software cd supporting literature cy3210-miniprog1 the cy3210-miniprog1 kit enables the user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc through a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 2 cy8c29466-24pxi 28-pdip chip samples 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread boarding space to meet all your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a devel- opment board for the cy8c24794-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunciator, and plenty of bread boarding space to meet all your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 25 of 34 development tools the development kits do not have on-board powerline capability, but can be used with a plc kit for development purposes. all development tools and development kits are sold at the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit can be used in conjunction with the plc kits to support in-circuit emulation. the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. psoc designer also supports the advanced emulation features. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240v power supply, euro-plug adapter imagecraft c compiler issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466-24pxi 28-pdip chip samples device programmers all device programmers are purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base 3 programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207 issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production programming environment. note that cy3207issp needs s pecial software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 26 of 34 ordering information the following table lists the cy8cplc10 plc device?s key package features and ordering codes. ordering code definitions table 20. cy8cplc10 plc device key features and ordering information package ordering code temperature range 28-pin (210 mil) ssop cy8cplc10-28pvxi ?40 c to +85 c 28-pin (210 mil) ssop (tape and reel) cy8cplc10-28pvxit ?40 c to +85 c cy 8 c plc 10 - xx xxx package type: thermal rating: pvx = ssop pb-free i = industrial pin count: 28 fixed function device family code: powerline communication solution technology code: c = cmos marketing code: 8 = cypress m8c core company id: cy = cypress [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 27 of 34 acronyms acronyms used ta b l e 2 1 lists the acronyms that are used in this document. reference documents designing an external host application for cypress? s powerline communication ic cy8cplc10 ? an52478 (001-52478) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . document conventions units of measure ta b l e 2 2 lists the unit sof measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). nu mbers not indicated by an ?h?, ?b?, or 0x are decimals. table 21. acronyms used in this datasheet acronym description acronym description ac alternating current led light-emitting diode biu band-in-use lpf low pass filter cmos complementary metal oxide semiconductor mips million instructions per second crc cyclic redundancy check pcb printed circuit board csma carrier sense multiple access pdip plastic dual-in-line package dc direct current plc powerline communication eeprom electrically erasable programmable read-only memory pll phase-locked loop fsk frequency-shift keying plt powerline transceiver gpio general-purpose i/o por power on reset i/o input/output psoc? programmable system-on-chip ice in-circuit emulator qfn quad flat no leads issp in-system serial programmi ng ssop shrink smal l-outline package lcd liquid crystal display usb universal serial bus table 22. units of measure symbol unit of measure symbol unit of measure c degree celsius mm millimeter khz kilohertz ms millisecond k kilohm mv millivolts mhz megahertz na nanoampere a microampere ns nanosecond f microfarad pf picofarad s microsecond v volts vrms microvolts root-mean-square w watt [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 28 of 34 glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). apis serve as building blocks for progr ammers that create software applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a common connection for a group of related devices. clock the device that generates a periodic signal with a fixed fr equency and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 29 of 34 compiler a program that translates a high level language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter performs the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connec t low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. glossary (continued) [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 30 of 34 ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces data into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning the device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a typical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. master device a device that controls the timing for data exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or more characteristi cs of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. glossary (continued) [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 31 of 34 port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is lower than a pre-set level. this is a type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device that sequentially shif ts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory . the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is synchronized by a clock signal. glossary (continued) [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 32 of 34 tri-state a function whose output can adopt three stat es: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued) [+] feedback
cy8cplc10 document number: 001-50001 rev. *k page 33 of 34 document history page document title: cy8cplc10 powerline communication solution document number: 001-50001 rev. ecn no. orig. of change submission date description of change ** 2606671 ghh/pyrs 11/13/08 new datasheet *a 2662761 ghh/aesa 02/20/09 added: - configurable baud rates and fsk frequencies - configurable rx gain *b 2748542 ghh/pyrs 08/05/2009 converted from preliminary to final modified: - memory map structure (added tx_gain register) - pinout (added option for external clocking: extclk) *c 2752799 ghh 08/17/2009 posting to external web. *d 2754780 ghh/pyrs 08/21/2009 added - optional external clock oscillator - suppy current for tx and rx modes removed - noise strength from memory map in table3 *e 2759000 ghh 09/02/2009 modified - dc power supply specifications added - dc modem specifications - ac modem specifications updated figures 5, 6, 7, 8, and 9. *f 2761019 gnkk 09/08/2009 corrected revision in page 1 *g 2778970 fre 10/05/2009 updated figure 1 and table 6 to state the requirement to use the external crystal for protocol timing table 6 and figure 10: changed pin 9 from nc to rsvd fixed minor typos *h 2846686 fre 01/12/2010 add table of contents. update copyright and sales urls. update 28-pin ssop package diagram. update dc gpio and ac chip-level specifications as follows: replace t ramp (time) with sr power_up (slew rate). replace t os and t osacc with t powerup . add i oh and i ol . *i 2903114 njf 04/01/2010 updated cypress website links added t baketemp and t baketime parameters updated package diagram *j 2938300 cgx 05/27/10 minor ecn to post to external website *k 3114960 njf 12/19/10 added dc i 2 c specifications table. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes was made to i 2 c timing diagram. it was updated for clearer understanding. removed footnote reference for ?solder reflow peak temperature? table. changed the t bufi2c parameter minimum from 1.3 to 500 s added a typical jc parameter to the thermal impedances table [+] feedback
document number: 001-50001 rev. *k revised january 6, 2011 page 34 of 34 psoc designer? and ez-color? are trademarks and psoc? is a registered trademark of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders, cy8cplc10 ? cypress semiconductor corporation, 2008-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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